Standard cells are generally produced using complementary metal oxide semiconductor (CMOS) technology, and may be pre-optimized cells saved in cell libraries. Thus, the designer of an integrated circuit may use standard cells by placing them and interconnecting them based upon the structure and functionality of the integrated circuit to be designed.
Conventional topology standard cells may be used down to a 28-nanometer technology node size, which corresponds to the line width, and generally corresponds to the channel length or gate width of a transistor produced in this technology. More precisely, conventional topology input/output standard cells, for example, may comprise n-channel metal-oxide-semiconductor field-effect (nMOS) transistors and p-channel metal-oxide-semiconductor field-effect (pMOS) transistors, and, in particular, the gate contacts may be placed on the gate lines of the cell between the active zones of the nMOS transistors and the active zones of the pMOS transistors. Moreover, the supply rails, for example, formed in the second metallization level M2, are placed at each end of the cell.
For sub-28-nanometer technology, the size of the contacts generally increases, and thus, it may then no longer be possible to place these contacts side by side on the parallel gate lines. Consequently, one approach includes staggering these gate contacts between the active zones of the nMOS transistors and the active zones of the pMOS transistors. However, design constraints would then require the size of these active zone regions, and therefore consequently, the performance of the transistors, to be reduced.